1. Field of the Invention
This invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit which includes shared sense amplifiers and is adapted for multibit parallel input and output configuration and for increasing the capacity.
2. Description of the Prior Art
In semiconductor memory circuits, the folded bit line structure in which a bit line for giving a reference potential to a sense amplifier (referred to as bit line for reference potential hereinafter) and a bit line for reading out data of a memory cell (referred to as bit line for read hereinafter) are arranged on one side of the sense amplifier, gives less induced noise to the bit line compared with the open bit line structure in which the bit line for reference potential and the bit line for read are arranged on the mutually opposite sides of the sense amplifier, so that it is currently in widespread use for semiconductor memory circuits.
Moreover, since in a semiconductor memory circuit such as a dynamic RAM (referred to as DRAM hereinafter) the ratio of the capacity of the memory cell capacitor (referred to as capacity of memory capacitor hereinafter) to the parasitic capacity of the bit line (referred to as capacity of bit line hereinafter) is related directly to the read voltage generated in the bit line, this ratio is an important parameter for the design of DRAM. The capacity of bit line is determined by the number, the size, and the structure of memory cells connected to the bit line, and the structure, size, material, or the like of the bit line itself. Accompanying the advancement of the generation of semiconductor memory circuits and the increase of the memory capacity, geometrical refinement of the memory cell and the bit line is advanced and the capacity of bit line is decreased. On the other hand, it brings about a decrease of the capacity of memory capacitor and an increase of the induced noise, and the number of the memory cells connected to one bit line has not been changed since it was increased from 64 bits to 128 bits for 256 kbit DRAM, even for the advances of the memory capacity of 1M bits, 4M bits, and 16M bits. Various kinds of split bit line modes have been proposed in order to keep the number of memory cells connected to one bit line constant, in the midst of the alternation of generation of DRAM as mentioned above, under the condition of limited chip size. Among them, the multisplit bit line shared sense amplifier mode (referred to as shared sense amplifier mode hereinafter) is being adopted most widely for the reasons that it is possible to realize a reduction of power consumption and an improvement of operating speed, and is most advantageous from the viewpoint of chip size (see for example, 16Mbit DRAM .mu.PD4216400 made by NEC Corporation which is the assigned of this application).
Next, an example of semiconductor memory circuit of the shared sense amplifier mode will be described.
This semiconductor memory circuit comprises a plurality of memory cell arrays each including a plurality of memory cell trains connected respectively to bit line pairs of folded bit line mode, and are arranged in the direction in which each of these memory cell train extends while keeping the mutual correspondence relation among these memory cell trains, a plurality of first selection/sense amplifier circuits each including first selection means which is arranged in every interarray regions between the pair of mutually adjacent memory cell arrays and selects for each member of the respective pairs either of an odd-numbered train or an even-numbered train of the plurality of memory cell trains of the memory cell arrays on both sides of the interarray region, a plurality of sense amplifiers which amplify the respective read data of the memory cell trains selected by the first selection means in one-to-one basis, and second selection means which selects one of the plurality of sense amplifiers and one of the memory cell trains selected by the first selection means and connect them to the corresponding data input and output lines, and transmits one of the amplified read data of an odd-numbered or an even-numbered memory cell train of the selected memory cell array on one side to the corresponding data input and output lines and supplies write data transmitted to the corresponding data input and output lines to a selected memory cell train of a selected memory cell array, two units of second selection/sense amplifier circuits each including a plurality of sense amplifiers arranged on the outside of the respective memory cell arrays at both ends of the disposition of the plurality of memory cell arrays and amplify in one-to-one basis read data of memory cell trains set differently from those of the first selection/sense amplifier circuits corresponding to the outermost memory cell arrays and selection means which selects one of the plurality of the sense amplifiers and one of the set memory cell trains of the outermost memory cell array and connects them to corresponding data input and output lines, and transmit amplified read data from the set memory cell trains of the outermost memory cell arrays to corresponding data input and output lines and supply write data transmitted to the corresponding data input and output lines to selected memory cell trains of the outermost memory cell arrays, a plurality of data buses corresponding to the respective bits of data which is transferred in bit parallel mode between an external circuit, and a plurality of input and output switching circuits which transmit the respective read data from the memory cell arrays one by one to the corresponding data buses via the first and the second selection/sense amplifier circuits by sequentially assigning equal number of memory cell arrays in the order of arrangement to the plurality of data buses, respectively, and supply write data transmitted to these data buses from the external circuit to respective selected memory cell trains of the corresponding memory cell arrays.
If it is assumed in this semiconductor memory circuit that, for example, the number of the memory cell arrays is eight, the number of the data buses is four, and the data transfer between the external circuit is carried out in four bit parallel mode, then seven first selection/sense amplifier circuits are arranged among eight memory cell arrays, a second selection/sense amplifier circuit is arranged on the outside of the each of the outermost memory cell array of the eight memory cell arrays, and a plurality of input and output switching circuits are arranged between the first and second selection/sense amplifier circuits and four data buses. Since two memory cell arrays each are made to correspond sequentially in the order of arrangement to the respective members of the four data buses, the first and the second memory cell arrays from the left correspond to the first data bus, the third and the fourth memory cell arrays correspond to the second data bus, the fifth and the sixth memory cell arrays correspond to the third data bus, and the seventh and the eighth memory cell arrays correspond to the fourth data bus. Further, if the first and the second selection/sense amplifier circuits are designated from the left as the first, the second, . . . , and the ninth sense amplifiers, the data transmission between the first and the second memory cell arrays and the first data bus is executed via the first, second, and the third selection/sense amplifier circuits, the data transmission between the third and the fourth memory cell arrays and the second data bus is executed via the third, the fourth, and the fifth selection/sense amplifier circuits, and similarly, the data transmission between the fifth and the sixth memory cell arrays and the third data bus is executed via the fifth, the sixth, and the seventh selection/sense amplifier circuits, and the data transmission between the seventh and the eighth memory cell arrays and the fourth data bus is executed via the seventh, the eighth and the ninth selection/sense amplifier circuits.
As in the above, in this semiconductor memory circuit, the third, the fifth, and the seventh selection/sense amplifier circuits have to carry out the data transfer between the respective two data buses. For this reason, it becomes necessary to have two input and output switching circuits between these selection/sense amplifier circuits and the data buses, and the layout becomes complicated and the chip area needs be increased accordingly.